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| 1 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g S2065 ? quad serial backplane device with dual i/o device specification features ? broad operating rate range (770 mhz - 1.3 ghz) - 1062 mhz (fibre channel) - 1250 mhz (gigabit ethernet) line rates - 1/2 rate operation ? quad transmitter incorporating phase-locked loop (pll) clock synthesis from low speed reference ? quad receiver pll provides independent clock and data recovery for each channel ? internally series terminated ttl outputs ? on-chip 8b/10b line encoding and decoding for four separate parallel 8 bit channels ? 32 bit parallel ttl interface ? low-jitter serial pecl interface ? local loopback ? interfaces with coax, twinax, or fiber optics ? single +3.3v supply, 2.7 w power dissipation ? compact 23mm x 23mm 208 tbga package ? redundant high speed transmit and receive serial interfaces applications high-speed data communications ? ethernet backbones ? workstation ? frame buffer ? switched networks ? data broadcast environments ? proprietary extended backplanes general description the S2065 facilitates high-speed serial transmission of data in a variety of applications including gigabit ethernet, fibre channel, serial backplanes, and pro- prietary point to point links. the chip provides four separate transceivers which can be operated indi- vidually or locked together for an aggregate data ca- pacity of >4 gbit/sec in each direction. the S2065 provides dual transmit and receive serial i/o. the dual transmit and receive serial i/o are useful for backbone applications in which redundant optical or electrical links are required. each bi-directional channel provides 8b/10b coding/ decoding, parallel to serial and serial to parallel con- version, clock generation/recovery, and framing. the on-chip transmit pll synthesizes the high-speed clock from a low-speed reference. the on-chip quad receive pll is used for clock recovery and data re- timing on the four independent data inputs. the transmitter and receiver each support differential pecl-compatible i/o for copper or fiber optic com- ponent interfaces with excellent signal integrity. re- dundant transmit and receive serial i/o are provided to support applications with redundant switch fabrics or line interfaces. local loopback mode allows for system diagnostics. the chip requires a 3.3v power supply and dissipates approximately 2.7 watts. figure 1 shows the use of the S2065 and s2066 in a gigabit ethernet application. figure 2 shows the use of a S2065 in a serial backplane application. figure 3 summarizes the input and output signals on the S2065. figures 4 and 5 show the transmit and receive block diagrams, respectively. figure 1. typical quad gigabit ethernet application mac (asic) quad gigabit ethernet interface mac (asic) mac (asic) mac (asic) to serial backplane ge interface serial bp driver to serial backplane s2066 S2065
2 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g figure 2. typical backplane application mac (asic) S2065 atm fibre channel ethernet etc. mac (asic) mac (asic) mac (asic) crosspoint switch #2 s2016 s2025 s2028 crosspoint switch #1 s2016 s2025 s2028 mac (asic) S2065 atm fibre channel ethernet etc. mac (asic) mac (asic) mac (asic) mac (asic) S2065 atm fibre channel ethernet etc. mac (asic) mac (asic) mac (asic) mac (asic) s2067 atm fibre channel ethernet etc. mac (asic) backplane signal group #1 backplane signal group #2 3 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g figure 3. S2065 input/output diagram 10 10 10 10 10 10 10 10 refclk tmode rate reset tclko dina[0:7] sofa, kgena dinb[0:7] sofb, kgenb dinc[0:7] sofc, kgenc dind[0:7] sofd, kgend tclka tclkb tclkc tclkd rca p/n rcb p/n rcc p/n rcd p/n douta[0:7] eofa, kflaga doutb[0:7] eofb, kflagb doutc[0:7] eofc, kflagc doutd[0:7] eofd, kflagd ch_lock clksel erra errb errc errd cmode tx1ap/n tx2ap/n tx1bp/n tx2bp/n tx1cp/n tx2cp/n tx1dp/n tx2dp/n rx1ap/n rx2ap/n rx1bp/n rx2bp/n rx1cp/n rx2cp/n rx1dp/n rx2dp/n rxsela rxselb rxselc rxseld lpen 4 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g figure 4. transmitter block diagram tmode 8b/10b encode 8 10 sofa kgena dina[0:7] tx2ap tx2an tx1ap tx1an txabp 8 shift reg 8b/10b encode 8 10 sofb kgenb dinb[0:7] tx2bp tx2bn tx1bp tx1bn txbbp 8 shift reg tclkb 8b/10b encode 8 10 sofc kgenc dinc[0:7] tx2cp tx2cn tx1cp tx1cn txcbp 8 shift reg tclkc 8b/10b encode 8 10 sofd kgend dind[0:7] tx2dp tx2dn tx1dp tx1dn txdbp 8 shift reg tclkd din pll 10x/20x refclk clksel ch_lock mux rate refclk tclko fifo (input) fifo (input) fifo (input) fifo (input) tclka 0123 0123 0123 0123 ch_lock tclkb testen tclkc 5 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g figure 5. receiver block diagram dout pll clock/data recovery dout pll clock/data recovery eofa kflaga erra douta[0:7] eofb kflagb errb doutb[0:7] fifo (output) dout pll clock/data recovery eofd kflagd errd doutd[0:7] dout pll clock/data recovery eofc kflagc errc doutc[0:7] refclk 8 10 8b/10b decode framing data stretching timing 8 8 8 8 rcap/n 2 rcbp/n 2 rccp/n 2 rcdp/n 2 cmode fifo (output) fifo (output) fifo (output) 8 8 8 10 10 10 lpen rx1ap rx1an rx2ap rx2an rxsela rx1bp rx1bn rx2bp rx2bn rxselb rx1dp rx1dn rx2dp rx2dn rxseld rx1cp rx1cn rx2cp rx2cn rxselc txdbp txcbp txbbp txabp tmode ch_lock 8b/10b decode framing data stretching timing 8b/10b decode framing data stretching timing 8b/10b decode framing data stretching timing rate 6 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g transmitter description the transmitter section of the S2065 contains a single pll which is used to generate the serial rate transmit clock for all transmitters. four channels are provided with a variety of options regarding input clocking and loopback. the transmitters can operate in the range of 770 mhz to 1.3 ghz, 10 or 20 times the reference clock frequency. the transmitter func- tions are shown schematically in figure 4. data input the S2065 has been designed to simplify the parallel interface data transfer and provide the utmost in flex- ibility regarding clocking of parallel data. prior, or less sophisticated, implementations of this function have either forced the user to synchronize transmit data to the reference clock or to provide the output clock as a reference to the pll, resulting in increased jitter at the serial interface. the S2065 incorporates a unique input structure, which enables the user to provide a clean reference source for the pll and to accept a separate external clock which is used exclusively to reliably clock data into the device. the S2065 also provides a system clock output, tclko, which is derived from the internal vco. the frequency of this output is constant at the parallel word rate, 1/10 the serial data rate, regardless of whether the reference is provided at 1/10 or 1/20 the serial data rate. this clock can be used by upstream circuitry as a system clock. data is input to each channel of the S2065 nominally as a 10-bit wide word. this consists of 8-bits of user data, kgen, and sof. an input fifo and a clock input, tclkx, are provided for each channel of the S2065. the device can operate in two different modes. in channel lock mode all four bytes of the input data are clocked into their respective fifos using a common clock. the S2065 can be configured to use either the tclka (tclk mode) input or the refclk input (refclk mode). in normal mode, each byte of data is clocked into its fifo with the tclkx provided with each byte. a ttl clock (tclko) at the parallel data rate is provided by the S2065 for use by upstream circuitry. the tclko is derived from the transmit vco. table 1 provides a summary of the input modes for the S2065. operation in the tclk mode makes it easier for users to meet the relatively narrow setup and hold time window required by the parallel 10-bit interface. the tclk signal is used to clock the data into an internal holding register and the S2065 synchronizes its internal data flow to ensure stable operation. the tclk is not used as a reference to the vco. this facilitates the provision of a clean reference clock resulting in minimum jitter on the serial output. the tclk must be frequency locked to refclk, but may have an arbitrary but fixed phase relationship. adjustment of internal timing of the S2065 is per- formed during reset. once synchronized, the S2065 can tolerate up to 3ns of phase drift between tclk and refclk. k c o l n a h ce d o m tn o i t a r e p o 00 r o f d e s u k l c f e r . e d o m k l c f e r l a m r o n ) . w e k s - e d e t y b r e v i e c e r o n ( . s l e n n a h c l l a 01 k c o l c o t d e s u x k l c t . e d o m k l c t l a m r o n ) . w e k s - e d e t y b r e v i e c e r o n ( . s o f i f l l a o t n i a t a d 10 . e d o m k l c f e r . e d o m k c o l l e n n a h c . s o f i f l l a o t n i a t a d k c o l c o t d e s u k l c f e r ) . e v i t c a w e k s - e d e t y b r e v i e c e r ( 11 . e d o m a k l c t . e d o m k c o l l e n n a h c . s o f i f l l a o t n i a t a d k c o l c o t d e s u a k l c t ) . e v i t c a w e k s - e d e t y b r e v i e c e r ( table 1. input modes note that internal synchronization of fifos is performed upon de-assertion of reset. 7 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g figure 6. din data clocking with tclk figure 7. fc/ge refclk din clocking refclk S2065 vco/10 or vco/20 tclkx dinx[0:7] ref oscillator mac asic tclko pll refclk S2065 tclkx dinx[0:7] ref oscillator mac asic tclko pll vco/10 the following figures illustrate the broad range of transmit data clocking options supported by the S2065. figure 6 demonstrates the flexibility afforded by the S2065. a low jitter reference is provided directly to the S2065 at either 1/10 or 1/20 the serial data rate. this ensures minimum jitter in the synthesized clock used for serial data transmission. a system clock output at the parallel word rate, tclko, is derived from the pll and provided to the upstream circuit as a system clock. this clock can be buffered as re- quired without concern about added delay. there is no phase requirement placed upon tclko and the tclkx clock, which is provided back to the S2065, other than that they remain within 3ns of the phase relationship established at reset. the S2065 also supports the traditional refclk (tbc) clocking found in fibre channel and gigabit ethernet applications and is illustrated in figure 7. this approach imposes significant challenges in maintaining timing margins on the designer. half rate operation the S2065 supports full and 1/2 rate operation for all modes of operation. when rate is low, the S2065 serial data rate equals the vco frequency. when rate is high, the vco is divided by 2 before being provided to the chip. thus, the S2065 can support fibre channel and serial backplane functions at both full and 1/2 the vco rate. 8b/10b coding the S2065 provides 8b/10b line coding for each chan- nel. the 8b/10b transmission code includes serial en- coding and decoding rules, special characters, and error control. information is encoded, 8 bits at a time, into a 10-bit transmission character. the characters defined by this code ensure that short run lengths and enough transitions are present in the serial bit stream to make clock recovery possible at the receiver. the encoding also greatly increases the likelihood of de- tecting any single or multiple errors that might occur during the transmission and reception of data 1 . the 8b/10b transmission code includes d-characters, used for data transmission, and k-characters, used for control or protocol functions. each d-character and k- character has a positive and a negative parity version. the parity of each codeword is selected by the en- coder to control the running disparity of the data stream. k-character generation is controlled individu- ally for each channel using the kgenx input. when kgen is asserted, the data on the parallel input is mapped into the corresponding control character. the parity of the k-character is selected to minimize run- ning disparity in the serial data stream. table 2 lists the k characters supported by the S2065 and identi- fies the mapping of the din[7:0] bits to each character. 1 a.x. widner and p.a. franaszek, "a byte-oriented dc bal- anced (0,4) 8b/10b transmission code," ibm research report rc9391, may 1982. 8 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g a special input is provided to simplify the generation of the k28.5 character. an sofx input is provided for each channel. when sof is asserted, the k28.5 character is generated regardless of the data on the parallel input. the k28.5 character can be of either positive or negative parity, depending on the current running disparity. when the chip is in channel lock mode, assertion of sofa causes the k28.5 to be generated on all four serial data streams, sofc is ignored. when sofd is asserted during chan- nel lock mode, this resets the channel lock state machine. table 3 shows the mapping of the 8b/10b characters representation. data is transmit- ted bit a or din[0] first. in addition to data and k characters, the S2065 can also generate a unique sync sequence consisting of 16 consecutive k28.5 characters. this event is initi- ated by the simultaneous assertion of kgenx and sofx for one clock period. the sofx and kgenx inputs should be held low until the sync sequence has completed. the sync sequence may start with either a positive or negative parity k28.5. (depending on the current running disparity.) the parity of the second and third k28.5 are inverse with respect to a valid 8b/ 10b sequence. parity of the remaining k28.5 alter- nate in accordance with the 8b/10b coding standard. thus, the parity of the k28.5 pattern consists of + + - - + - + - + - + - + - + - or - - + + - + - + - + - + - + - +. tables 4 and 4a show the transmitter control signals for both normal and channel lock mode. table 2. k character generation (sofx = 0) k r e t c a r a h c ] 0 : 7 [ n i dn e g k + d r t n e r r u c- d r t n e r r u c s t n e m m o c j h g f i e d c b aj h g f i e d c b a 0 . 8 2 k 1 . 8 2 k 2 . 8 2 k 3 . 8 2 k 4 . 8 2 k 5 . 8 2 k 6 . 8 2 k 7 . 8 2 k 7 . 3 2 k 7 . 7 2 k 7 . 9 2 k 7 . 0 3 k 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 r e t c a r a h c c n y s 9 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g table 3. data to 8b/10b alphabetic representation e t y b a t a d r o ] 9 : 0 [ n i d ] 9 : 0 [ t u o d 0123456789 . r p e r . h p l a b 0 1 / b 8 abcdei fghj x f o sx n e g kt u p t u o n i d 5 6 0 2 s 00 a t a d l e l l a r a p d e d o c n e 01 d n a 2 e l b a t y b d e n i f e d s a r e t c a r a h c - k ] 0 : 7 [ n i d 10 r e t c a r a h c 5 . 8 2 k 11 , r e t c a r a h c d r o w 6 1 l a i c e p s + - + - + - + + - - r o - + - + - + - + - + - + - - + + + - + - + - table 4. transmitter control signals (normal mode, ch_lock = 0) table 4a. transmitter control signals (channel lock mode, ch_lock = 1) a f o sb f o sx n e g kt u p t u o 5 6 0 2 s 000 . a t a d l e l l a r a p d e d o c n e 001 . x l e n n a h c n o 2 e l b a t y b d e n i f e d s a r e t c a r a h c k 100 . s l e n n a h c r u o f l l a n o r e t c a r a h c 5 . 8 2 k 101 . x l e n n a h c n o r e t c a r a h c c n y s d r o w 6 1 l a i c e p s x1x r u o f l l a n o r e t c a r a h c c n y s d r o w 6 1 l a i c e p s . s l e n n a h c 10 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g frequency synthesizer (pll) the S2065 synthesizes a serial transmit clock from the reference signal provided. the S2065 will obtain phase and frequency lock within 2500 bit times after the start of receiving reference clock inputs. reliable locking of the transmit pll is assured, but a lock- detect output is not provided. reference clock input the reference clock input must be supplied with a low-jitter clock source. all reference clocks in a sys- tem must be within 200 ppm of each other to ensure that the clock recovery units can lock to the serial data. the frequency of the reference clock must be either 1/10 the serial data rate, clksel = 0, or 1/20 the serial data rate, clksel = 1. note that in both cases the frequency of the parallel word rate output, tclko, is constant at 1/10 the serial data rate. serial data outputs two high-speed differential outputs are provided for each channel. this enables each channel to drive a primary and secondary switch fabric for backplane applications in which redundancy is required to achieve higher reliability or hot-swappability. the pri- mary and secondary high speed outputs remain ac- tive except when the loopback mode is enabled. each high speed output should be provided with a resistor to vss (gnd) near the device. a value of 4.5k w provides optimal performance with minimum impact on power dissipation. the resistance may be as low as 450 w , but will dissipate additional power with no substantive performance improvement. outputs are designed to perform optimally when ac-coupled. when operating in the chan nel lock mode, the user must ensure that the path length of the four high speed serial data signals are matched to within 50 se- rial bit times of delay. failure to meet this requirement may result in bit errors in the received data or in byte misalignment. in addition to path length induced tim- ing skew, the S2065 can tolerate up to 3 ns of phase drift between channels after deskewing the outputs. test functions the S2065 can be configured for factory test to aid in functional testing of the device. when in the test mode, the internal transmit and receive voltage-con- trolled oscillator (vco) is bypassed and the refer- ence clock substituted. this allows full functional testing of the digital portion of the chip or bypassing the internal synthesized clock with an external clock source. (see the section other operating modes.) transmit fifo initialization the transmit fifo must be initialized after stable delivery of data and tclk to the parallel interface, and before entering the normal operational state of the circuit. fifo initialization is performed upon the de-assertion of the reset signal. the din fifo is automatically reset upon power up immediately after the din pll obtains stable frequency lock. if the circuit has not reached steady state timing at this point, then the user must initialize by asserting the reset signal. the tclko output will operate nor- mally even when reset is asserted and is available for use as an upstream clock source. table 5. operating rates e t a rl e s k l c k l c f e r y c n e u q e r f t u p t u o l a i r e s e t a r o k l c t y c n e u q e r f 00 0 1 / r d sz h g 3 . 1 C 7 7 . 00 1 / r d s 01 0 2 / r d sz h g 3 . 1 C 7 7 . 00 1 / r d s 10 0 1 / r d sz h g 5 6 . 0 - 9 3 . 00 1 / r d s 11 0 2 / r d sz h g 5 6 . 0 - 9 3 . 00 1 / r d s note: sdr = serial data rate. 11 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g receiver description each receiver channel is designed to implement a serial backplane receiver function through the physi- cal layer. a block diagram showing the basic func- tion is provided in figure 5. whenever a signal is present, the receiver attempts to recover the serial clock from the received data stream. after acquiring bit synchronization, the S2065 searches the serial bit stream for the occur- rence of a k28.5 character on which to perform word synchronization. once synchronization on both bit and word boundaries is achieved, the receiver pro- vides the decoded data on its parallel outputs. the S2065 has the ability to operate with all four channels locked together (channel lock mode). the channel lock process and status reporting is de- scribed later in this document. data input two differential receivers are provided for each chan- nel of the S2065. this supports switching between redundant switch fabrics for serial backplane applica- tions. each channel has a loopback mode in which the serial data from the transmitter replaces serial in- put data. the loopback function for all four channels is controlled by the loopback enable signal, lpen. the high speed serial inputs to the S2065 are inter- nally biased to vdd-1.3v to simplify ac-coupling of the differential inputs and allow differential termina- tion with a single resistor. clock recovery function clock recovery is performed on the input data stream for each channel of the S2065. the receiver pll has been optimized for the anticipated needs of serial backplane systems. a simple state machine in the clock recovery macro decides whether to acquire lock from the serial data input or from the reference clock. the decision is based upon the frequency and run length of the serial data inputs. if at any time the frequency or run length checks are violated, the state machine forces the vco to lock to the refer- ence clock. this allows the vco to maintain the cor- rect frequency in the absence of data. the lock to reference frequency criteria insure that the S2065 will respond to variations in the serial data input frequency (compared to the reference fre- quency). the new lock state is dependent upon the current lock state, as shown in table 6. the run-length criteria insure that the S2065 will re- spond appropriately and quickly to a loss of signal. the run-length checker flags a condition of consecu- tive ones or zeros across 12 parallel words. thus 119 or less consecutive ones or zeros does not cause signal loss, 129 or more causes signal loss, and 120 - 128 may or may not, depending on how the data aligns across byte boundaries. if both the off-frequency detect circuitry test and the run-length test are satisfied, the cru will attempt to lock to the incoming data. when lock is achieved, lock-det is asserted on the err, eof, and kflag status lines. it is possible for the run length test to be satisfied due to noise on the inputs, even if no signal is present. in this case the lock detect sta- tus may periodically assert as the vco frequency approaches that of the refclk. in any transfer of pll control from the serial data to the reference clock, the rcxp/n outputs remain phase continuous and glitch free, assuring the integ- rity of downstream clocking. when operating in independent mode, all four pll lock status is indicated by a 1-0-1 on the err, eof, and kflag outputs, respectively. when operating in the channel lock mode, pll locking of all four channels must be accomplished before byte-skewing is achieved and in sync status is indicated on the err, eof, and kflag outputs. k c o l t n e r r u c e t a t se t a t s e t a t s e t a t se t a t s y c n e u q e r f l l p ) k l c f e r . s v () k l c f e r . s v ( ) k l c f e r . s v ( ) k l c f e r . s v () k l c f e r . s v ( e t a t s k c o l w e n d e k c o l m p p 8 8 4 12 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g reference clock input the reference clock must be provided from a low jitter clock source. the frequency of the received data stream (divided-by-10 or 20) must be within 200 ppm of the reference clock to ensure reliable locking of the receiver pll. a single reference clock is pro- vided to both the transmitter and the receiver of the S2065. serial to parallel conversion once bit synchronization has been attained by the S2065 cru, the S2065 must synchronize to the 10 bit word boundary. word synchronization in the S2065 is accomplished by detecting and aligning to the 8b/10b k28.5 codeword. the S2065 will detect and byte-align to either polarity of the k28.5. each channel of the S2065 will detect and align to a k28.5 anywhere in the data stream. two modes of opera- tion are supported. for normal mode operation, the presence of a k28.5 is indicated for each chan- nel by the assertion of the eofx signal. for channel lock operation, the S2065 must provide an additional level of synchronization to en- sure that differences in delay encountered by the four channels do not result in parallel output data from each channel leading or lagging by one parallel clock cycle. when in channel lock mode, asser- tion of sofa results in the k28.5 being transmitted simultaneously on all four channels. each receiver provides a fifo buffer and adjusts the delay through this buffer to ensure that the first data following the k28.5 is output simultaneously from the receiver on the parallel interface. the reception of a k28.5 char- acter is indicated on the eofa signal. table 8 de- tails the function of the eof, kflag, and err pins in status reporting. for channel lock operation, a single output clock, rcap/n, is provided synchro- nous with the data. the other rcxp/n clocks will be frequency locked, but will have an arbitrary phase relationship with the data. incidental errors occurring in the received data can transform a normal data character into a k28.5 char- acter. to prevent this occurrence from causing a single channel from attempting word re-alignment, possibly resulting in loss of channel lock, the S2065 implements a state machine which controls the syn- chronization process when operating in the chan- nel lock mode. note that when operating in the channel lock mode, the tclk[b:d] inputs must be tied low. fail- ure to do this will result in improper operation of the S2065. channel lock mode synchronization incidental errors occurring in the received data can transform a normal data character into a k28.5 char- acter. to prevent this occurrence from making the channel locking process unnecessarily vulnerable to bit errors, the S2065 implements a channel lock state machine for each channel with linkage between channels to move to the final de-skewed state. the channel lock state diagram is shown in figure 8. the S2065 powers up in the no sync state. when in the no sync state, each channel of the S2065 is actively searching the received data stream for the occurrence of a k28.5 and will align its de- multiplexor to the character when detected, and will enter the acquiring sync state. k28.5 will be re- ported on each channel as 0-1-1 (err-eof-kflag). when four or more consecutive k28.5 characters are received on a given channel, the channel will enter the re-sync state as shown in figure 8. "re-sync" state status will not be reported as 1-1-1 until the first valid data character has been received. if all four channels are in the "re-sync" state and each has received a valid data character within the deskew time of 5 bytes, then the S2065 will channel lock by aligning the data output from each channel such that the first valid data character for each chan- nel is output simultaneously. the device will move to the in sync state and indicate channel lock status by each channel as a 0-1-0. note that re-sync is reported independently by each channel regardless of the state of the other channels. however, in sync can only be reported when all four channels are in the in sync state and detect a valid data character within the deskew window. the in sync state is reported for each as 0-1-0. once the S2065 has entered the in sync state, it will report status but will not alter the relative skew of the output fifos. the S2065 will exit the in sync state and move to the no sync state if one of the four crus reports a loss of lock, if the 8b/10b decoder observes four consecutive decoding errors, or if the decoder error rate >50% in a block of 16 codewords. the device can also be put in the no sync state by setting sofd=low, asserting reset, or by momen- tarily de-asserting ch_lock signal. sofd is used to reset the channel lock state ma- chine and provides minimum disruption of the data path. when not in channel lock mode, the linkage be- tween the four state machines is broken and each channel operates independently. 13 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g figure 8. channel lock state machine loss of channel lock will be reported as indicated in figure 9 and table 8 by a 1-0-1 on the err, eof, and kflag signals, respectively. this is during the no sync state. the status lines will reflect the status of the individual channels and the device will respond to appropriate channel locking sequences and deskew as necessary. persistence of 1-0-1 status on any channel is indicative of cru lock failure, most likely resulting from loss of receiver input signal. the device will then respond to the channel locking se- quence. when operating in the channel lock mode, the tclk[b-d] inputs must be tied low. channel locking/re-locking procedure the channel locking/relocking procedures are sum- marized below. following these procedures will in- sure proper channel lock operation of the device. when powered up, the S2065 will lock to the received data within approximately 2500 bit times. the cru must report lock for approximately 32,000 refclk periods (320 m s) before channel locking is enabled. 1. ensure that the S2065 is in the no sync state. this can be accomplished by resetting the device by toggling sofd low, or by de-asserting the channel lock for several clock periods and then re-asserting. 2. transmit the appropriate synchronization se- quence. four k28.5 characters or the 16 word sync sequence can be used to de-skew the dout fifos. the 16 word sync character can be generated by asserting sofx=1 and kgenx=1. 3. wait for channel lock detected as defined by table 8. the S2065 will enter the no sync state if: any cru loses lock, if the ch_lock signal is de-asserted, if four or more consecutive decoder errors are ob- served, or if the decoder error rate exceeds 50% in a block of 16 bytes, or if sofd is low. if desired, the cru lock status of each channel can be checked by de-asserting ch_lock and confirming that loss of sync status (table 8) is not reported by any chan- nel. to reacquire sync after moving to the no sync state, repeat steps 2 and 3 above. re-sync no sync in sync all four channels in re-sync with valid data within deskew window errored codeword or valid data outside deskew window cru loss of lock or four sequential decoding errors or decoding error rate > 50% (block 16) reset acquiring sync one k28.5 detected 3 4 k28.5 detected errored codeword or <4 k28.5 or sofd = low sofd = low or or sofd = low 14 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g figure 9. channel locking synchronization timing (internal) resync a (internal) resync b (internal) resync c (internal) resync d (internal) deskewed resync a (internal) deskewed resync b (internal) deskewed resync c (internal) deskewed resync d fifo deskewing .... .... .... .... .... .... .... .... fifo deskewed (internal) channel lock a,b,c,d .... erra eofa kflaga rx data out .... .... .... .... bc (k28.5) valid data bc (k28.5) bc (k28.5) bc (k28.5) bc valid data bc bc bc 0 1 0 0 1 1 0 1 0 *note 1 1. the first three k28.5's will be reported as "k28.5" (011), subsequent k28.5 will be reported as "resync" or channel lock det ected." see table 8. 15 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g 8b/10b decoding after performing serial-to-parallel conversion, the S2065 provides 8b/10b decoding of the data. the received 10-bit codeword is decoded to recover the original 8-bit data. the decoder also checks for er- rors and flags, either invalid codeword errors or run- ning disparity errors by assertion of the errx signal. error type is determined by examining the eof out- put in accordance with table 8. when more than one reportable condition occurs simultaneously, reporting is in accordance with the rank assigned by table 8. data output data is output on the dout[0:7] outputs. k-charac- ters are flagged using the kflag signal. the eof (with kflag) is used to indicate the reception of a valid k28.5 character. invalid codewords and decod- ing errors are indicated on the err output. kflag, eof, and err are buffered with the data in the fifo to ensure that all outputs are synchronized at the S2065 outputs. errors are reported indepen- dently for each channel in both channel lock mode and normal mode operation. the S2065 ttl outputs are optimized to drive 65 w line impedances. internal source matching provides good performance on unterminated lines of reason- able length. parallel output clock rate two output clock modes are supported. when cmode is high, a complementary ttl clock at the data rate is provided on the rcxp/n outputs. data should be clocked on the rising edge of rcxp. when cmode is low, a complementary ttl clock at 1/2 the data rate is provided. data should be latched on the rising edge of rcxp and the rising edge of rcxn. the S2065 will operate properly when multiple k28.5 characters are received. byte alignment is achieved after the first k28.5 is received. the rcxp/n clock operates without glitches or loss of cycles. e d o me d o m c. q e r f n / p x c r e d o m k c o l c f l a h00 2 / o c v e d o m k c o l c l l u f10 1 / o c v table 7. output clock modes 16 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g r r ef o eg a l f kn o i t p i r c s e dk n a r 00 0 r e t c a r a h c a t a d d i l a v a t a h t s e t a c i d n i . r e t c a r a h c l a m r o n . d e t c e t e d n e e b s a h 6 00 1 r e t c a r a h c k a t a h t s e t a c i d n i . ) 5 . 8 2 k t o n ( r e t c a r a h c k . d e t c e t e d n e e b s a h 5 . 8 2 k n a h t r e h t o 6 01 0 d r o w l e l l a r a p e n o r o f s t r e s s a . d e t c e t e d k c o l l e n n a h c r u o f l l a t a h t s l a n g i s a g a l f k d n a a f o e , a r r e e h t n o n i h t i w e c n e u q e s c n y s - e r e h t d e i f i t n e d i e v a h s l e n n a h c . w o d n i w w e k s - e d e t y b e h t 2 01 1 f o r e t c a r a h c 5 . 8 2 k a t a h t s e t a c i d n i . - 5 . 8 2 k r o + 5 . 8 2 k . d e t c e t e d n e e b s a h y t i r a p y r a r t i b r a 6 10 0 t o n d r o w a t a h t s e t a c i d n i . n o i t a l o i v d r o w e d o c s a h g n i p p a m x . x k r o x . x d d i l a v y n a o t g n i d n o p s e r r o c . d e v i e c e r n e e b 4 10 1 e t a c i d n i o t d r o w l e l l a r a p e n o r o f s t r e s s a . c n y s f o s s o l f o s s o l n i s t l u s e r h c i h w d e r r u c c o s a h n o i t i d n o c a t a h t , e d o m t n e d n e p e d n i e h t n i g n i t a r e p o n e h w . k c o l l e n n a h c . k c o l t i b u r c f o s s o l s e t a c i d n i 1 11 0 g n i n n u r a t a h t s e t a c i d n i . ) 5 . 8 2 k n o e r o n g i ( r o r r e y t i r a p . d e v r e s b o n e e b s a h r o r r e y t i r a p s i d 5 11 1 l e l l a r a p e n o r o f s t r e s s a . ) x . x d + 4 x 5 . 8 2 k ( c n y s - e r s r e t c a r a h c 5 . 8 2 k e v i t u c e s n o c r u o f t a h t g n i t a c i d n i d r o w . d e v i e c e r n e e b s a h r e t c a r a h c x . x d d i l a v a y b d e w o l l o f d n a y l t n e d n e p e d n i n o i t i d n o c s i h t s t r o p e r l e n n a h c h c a e e h t n i h t i w c n y s - e r e h t y f i t n e d i t s u m s l e n n a h c r u o f l l a e b n a c k c o l l e n n a h c e r o f e b e m i t w e k s - e d e t y b d e w o l l a k c o l l e n n a h c h t i w d e t a c i d n i e b d n a d e v e i h c a . ) e v o b a e e s ( d e t c e t e d 3 table 8. error and status reporting 17 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g figure 10. S2065 diagnostic loopback other operating modes operating frequency range the S2065 is designed to operate at serial baud rates of 770 mhz to 1.3 ghz (616 mbit/sec to 1000 mbit/sec user data rate). the part is specified at the fibre channel rate (1062 mhz) and the gigabit ethernet rate (1.25 ghz), but will operate satisfacto- rily at any rate in this range. loopback mode when loopback mode is enabled, the serial data from the transmitter is provided to the serial input of the receiver. loopback mode can be simultaneously enabled for all four channels using the loopback-en- able input, lpen. the loopback mode provides the ability to perform system diagnostics and off-line testing of the inter- face to guarantee the integrity of the serial channel before enabling the transmission medium. loopback is enabled when lpen = 1. the high speed serial outputs are disabled when loopback operation is enabled. test modes the S2065 has a testability input to aid in functional testing of the device. the test mode is entered when ch_lock is high and tclkb is high. thus users must take care to ensure that tclk[b-d] are held low when operating in the channel locked mode. the following conditions are asserted when in test mode: 1. refclk replaces the vco clk (it also still goes to the transmit clock mux). 2. tclka clocks all 4 transmit channels. 3. tclkc is muxed in as the lock detect refclk for test purposes. 4. tclkd becomes the channel lock signal to the whole of the chip except the transmit clock. the reset pin is used to initialize the transmit fifos and must be asserted (low) prior to entering the normal operational state (see section transmit fifo initialization). note that reset does not disable the tclko output unless the tclkb input is high. output disabled cru csu 18 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g table 9. transmitter input signals assignment and description e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 7 a n i d 6 a n i d 5 a n i d 4 a n i d 3 a n i d 2 a n i d 1 a n i d 0 a n i d l t ti 2 1 p 2 1 r 3 1 t 2 1 t 3 1 u 1 1 p 1 1 r 1 1 t d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . a l e n n a h c r o f a t a d t i m s n a r t ) . 1 e l b a t e e s ( . k l c f e r r o a k l c t f o e g d e g n i s i r e h t n o n i a f o sl t ti 5 1 uf o r e t c a r a h c 5 . 8 2 k e h t s e s u a c h g i h a f o s . a e m a r f f o t r a t s n e h w . s t u p t u o a l e n n a h c n o d e t t i m s n a r t e b o t y t i r a p e t a i r p o r p p a 5 . 8 2 k e h t s e s u a c h g i h a f o s , e d o m k c o l l e n n a h c n i r u o f l l a n o d e t a r e n e g e b o t y t i r a p e t a i r p o r p p a f o r e t c a r a h c . s l e n n a h c a n e g kl t ti 4 1 un o a t a d e h t s e s u a c h g i h a n e g k . n o i t a r e n e g r e t c a r a h c - k . r e t c a r a h c - k a o t n i d e d o c n e e b o t ] 7 : 0 [ a n i d a k l c tl t ti 2 1 ud e s u s i l a n g i s s i h t , h g i h s i e d o m t n e h w . a k c o l c a t a d t i m s n a r t . 5 6 0 2 s e h t o t n i a f o s d n a , a n e g k , ] 7 : 0 [ a n i d n o a t a d k c o l c o t . d e r o n g i s i a k l c t , w o l s i e d o m t n e h w 7 b n i d 6 b n i d 5 b n i d 4 b n i d 3 b n i d 2 b n i d 1 b n i d 0 b n i d l t ti 5 1 r 4 1 p 5 1 t 4 1 r 7 1 u 6 1 u 3 1 p 4 1 t n i d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . b l e n n a h c r o f a t a d t i m s n a r t ) . 1 e l b a t e e s ( . k l c f e r r o , b k l c t , a k l c t f o e g d e g n i s i r e h t n o b f o sl t ti 6 1 rf o r e t c a r a h c 5 . 8 2 k e h t s e s u a c h g i h b f o s . b e m a r f f o t r a t s n e h w . s t u p t u o b l e n n a h c n o d e t t i m s n a r t e b o t y t i r a p e t a i r p o r p p a d r o w 6 1 l a i c e p s s e s u a c h g i h = b f o s , e d o m k c o l l e n n a h c n i . d e t a r e n e g e b o t x l e n n a h c n o r e t c a r a h c c n y s b n e g kl t ti 6 1 tn o a t a d e h t s e s u a c h g i h b n e g k . n o i t a r e n e g r e t c a r a h c - k . r e t c a r a h c - k a o t n i d e d o c n e e b o t ] 7 : 0 [ b n i d b k l c tl t ti 3 1 rd e s u s i l a n g i s s i h t , h g i h s i e d o m t n e h w . b k c o l c a t a d t i m s n a r t . 5 6 0 2 s e h t o t n i b f o s d n a , b n e g k , ] 7 : 0 [ b n i d n o a t a d k c o l c o t r o f " s e d o m t s e t " e e s ( . d e r o n g i s i b k l c t , w o l s i e d o m t n e h w ) . b k l c t g n i d r a g e r n o i t a m r o f n i l a n o i t i d d a 7 c n i d 6 c n i d 5 c n i d 4 c n i d 3 c n i d 2 c n i d 1 c n i d 0 c n i d l t ti 5 1 m 6 1 n 4 1 m 7 1 r 6 1 p 5 1 n 7 1 t 4 1 n n i d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . c l e n n a h c r o f a t a d t i m s n a r t ) . 1 e l b a t e e s ( . k l c f e r r o , c k l c t , a k l c t f o e g d e g n i s i r e h t n o note. all ttl inputs except refclk have internal pull-up networks. 19 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g table 9. transmitter input signals assignment and description (continued) e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d c f o sl t ti 7 1 nf o r e t c a r a h c 5 . 8 2 k e h t s e s u a c h g i h c f o s . c e m a r f f o t r a t s n i . s t u p t u o c l e n n a h c n o d e t t i m s n a r t e b o t y t i r a p e t a i r p o r p p a . d e r o n g i s i c f o s , e d o m k c o l l e n n a h c c n e g kl t ti 7 1 pn o a t a d e h t s e s u a c h g i h c n e g k . n o i t a r e n e g r e t c a r a h c - k . r e t c a r a h c - k a o t n i d e d o c n e e b o t ] 7 : 0 [ c n i d c k l c tl t ti 5 1 pd e s u s i l a n g i s s i h t , h g i h s i e d o m t n e h w . c k c o l c a t a d t i m s n a r t . 5 6 0 2 s e h t o t n i c f o s d n a , c n e g k , ] 7 : 0 [ c n i d n o a t a d k c o l c o t . d e r o n g i s i c k l c t , w o l s i e d o m t n e h w 7 d n i d 6 d n i d 5 d n i d 4 d n i d 3 d n i d 2 d n i d 1 d n i d 0 d n i d l t ti 7 1 l 6 1 k 5 1 k 4 1 k 7 1 m 6 1 l 6 1 m 5 1 l n i d e k c o l c s i s u b s i h t n o a t a d l e l l a r a p . d l e n n a h c r o f a t a d t i m s n a r t ) . 1 e l b a t e e s ( . k l c f e r r o , d k l c t , a k l c t f o e g d e g n i s i r e h t n o d f o sl t ti 6 1 jf o r e t c a r a h c 5 . 8 2 k e h t s e s u a c h g i h d f o s . d e m a r f f o t r a t s n i . s t u p t u o d l e n n a h c n o d e t t i m s n a r t e b o t y t i r a p e t a i r p o r p p a e h t s t e s e r s i h t , w o l = d f o s n e h w , e d o m k c o l l e n n a h c . e n i h c a m e t a t s k c o l l e n n a h c d n e g kl t ti 7 1 kn o a t a d e h t s e s u a c h g i h d n e g k . n o i t a r e n e g r e t c a r a h c - k . r e t c a r a h c - k a o t n i d e d o c n e e b o t ] 7 : 0 [ d n i d d k l c tl t ti 4 1 ld e s u s i l a n g i s s i h t , h g i h s i e d o m t n e h w . d k c o l c a t a d t i m s n a r t . 5 6 0 2 s e h t o t n i d f o s d n a , d n e g k , ] 7 : 0 [ d n i d n o a t a d k c o l c o t . d e r o n g i s i d k l c t , w o l s i e d o m t n e h w note. all ttl inputs except refclk have internal pull-up networks. 20 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g table 10. transmitter output signals assignment and description e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p a 1 x t n a 1 x t . f f i d l c e p v l o7 1 a 7 1 b . a l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a m i r p p a 2 x t n a 2 x t . f f i d l c e p v l o4 1 e 6 1 d . a l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a d n o c e s p b 1 x t n b 1 x t . f f i d l c e p v l o7 1 c 7 1 d . b l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a m i r p p b 2 x t n b 2 x t . f f i d l c e p v l o4 1 f 5 1 f . b l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a d n o c e s p c 1 x t n c 1 x t . f f i d l c e p v l o6 1 f 7 1 e . c l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a m i r p p c 2 x t n c 2 x t . f f i d l c e p v l o5 1 g 4 1 g . c l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a d n o c e s p d 1 x t n d 1 x t . f f i d l c e p v l o7 1 f 7 1 g . d l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a m i r p p d 2 x t n d 2 x t . f f i d l c e p v l o4 1 h 5 1 h . d l e n n a h c r o f s t u p t u o l a i r e s d e e p s h g i h y r a d n o c e s o k l c tl t to 4 1 jd e d i v o r p s i k c o l c s i h t . e t a r a t a d l e l l a r a p e h t t a k c o l c t u p t u o l t t . y r t i u c r i c m a e r t s - p u y b e s u r o f 21 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g table 11. mode control signals assignment and description note. all ttl inputs except refclk have internal pull-up networks. e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d k c o l _ h cl t ti4 er u o f l l a s k c o l h g i h k c o l l e n n a h c . l o r t n o c e d o m k c o l l e n n a h c ) . 1 e l b a t e e s ( . r e h t e g o t s l e n n a h c e d o m tl t ti 3 1 bd e s u s i k l c f e r , w o l s i e d o m t n e h w . l o r t n o c e d o m t i m s n a r t . 5 6 0 2 s e h t o t n i x n e g k d n a , x f o s , ] 7 : 0 [ x n i d n o a t a d k c o l c o t e h t o t n i a t a d k c o l c o t d e s u s i x k l c t , h g i h s i e d o m t n e h w y b d e k c o l c e r a s l e n n a h c r u o f l l a , e d o m k c o l l e n n a h c n i . 5 6 0 2 s l e n n a h c h c a e , ) w o l k c o l _ h c ( e d o m t n e d n e p e d n i n i . a k l c t . k l c t e v i t c e p s e r s t i y b d e k c o l c s i l e s k l cl t ti 2 1 ce h t r o f l l p e h t s e r u g i f n o c l a n g i s s i h t . t u p n i t c e l e s k l c f e r e h t , 0 = l e s k l c n e h w . y c n e u q e r f k l c f e r e t a i r p o r p p a n e h w . e t a r d r o w l e l l a r a p e h t l a u q e d l u o h s y c n e u q e r f k l c f e r l e l l a r a p e h t 2 / 1 e b d l u o h s y c n e u q e r f k l c f e r e h t , 1 = l e s k l c . e t a r a t a d k l c f e rl t ti 7 1 hy c n e u q e r f d n a o c v t i m s n a r t e h t r o f d e s u s i k c o l c e c n e r e f e r . a t a d l a i r e s r e v i e c e r e h t m o r f d e r e v o c e r k c o l c e h t r o f k c e h c t e s e rl t ti 5 1 cd e c r o f s i l l p r e v i e c e r e h t . t e s e r n i d l e h s i 5 6 0 2 s e h t , w o l n e h w e g d e g n i s i r e h t n o d e z i l a i t i n i e r a s o f i f e h t . k l c f e r e h t o t k c o l o t . y l l a m r o n s e t a r e p o 5 6 0 2 s e h t , h g i h n e h w . t e s e r f o e t a rl t ti 2 1 dl a u q e e t a r t u p t u o l a i r e s e h t h t i w s e t a r e p o 5 6 0 2 s e h t , w o l n e h w e h t h t i w s e t a r e p o 5 6 0 2 s e h t , h g i h n e h w . y c n e u q e r f o c v e h t o t . s n o i t c n u f l l a r o f 2 y b d e d i v i d y l l a n r e t n i o c v 22 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g table 12. receiver output signal pin assignment and description e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 7 a t u o d 6 a t u o d 5 a t u o d 4 a t u o d 3 a t u o d 2 a t u o d 1 a t u o d 0 a t u o d l t to1 j 3 j 2 j 1 h 2 h 3 h 1 f 2 g d i l a v s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r a l e n n a h c e h t n o d i l a v d n a e d o m k c o l c l l u f n i p a c r f o e g d e g n i s i r e h t n o . e d o m k c o l c f l a h n i n a c r d n a p a c r h t o b f o e g d e g n i s i r a f o el t to2 fs e t a c i d n i t u p t u o s i h t n o h g i h a . d e t c e t e d e m a r f f o d n e a l e n n a h c l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b s a h 5 . 8 2 k d i l a v a t a h t ) . 8 e l b a t e e s ( . ] 7 : 0 [ a t u o d s t u p t u o a t a d a g a l f kl t to3 ga t a h t s e t a c i d n i a g a l f k n i h g i h a . g a l f r e t c a r a h c - k a l e n n a h c e h t n o t n e s e r p a t a d . d e t c e t e d n e e b s a h r e t c a r a h c l o r t n o c d i l a v h c i h w e t a c i d n i o t d e s u e b d l u o h s ] 7 : 0 [ a t u o d e c a f r e t n i l e l l a r a p ) . 8 e l b a t e e s ( . d e v i e c e r s a w r e t c a r a h c a r r el t to1 ge h t s e i f i n g i s a r r e n o h g i h a . r o r r e e v i e c e r a l e n n a h c r o r r e d r o w e d o c d i l a v n i n a r o r o r r e y t i r a p a r e h t i e f o e c n e r r u c c o ) . 8 e l b a t e e s ( . a t a d d e v i e c e r e h t f o g n i d o c e d g n i r u d p a c r n a c r l t to2 k 1 k , a f o e , ] 7 : 0 [ a t u o d , a t a d e v i e c e r l e l l a r a p . k c o l c a t a d e v i e c e r n e h w p a c r f o e g d e g n i s i r e h t n o d i l a v e r a a r r e d n a , a g a l f k d n a p a c r h t o b f o e g d e g n i s i r e h t n o d i l a v d n a e d o m k c o l c l l u f n i . e d o m k c o l c f l a h n i n a c r 7 b t u o d 6 b t u o d 5 b t u o d 4 b t u o d 3 b t u o d 2 b t u o d 1 b t u o d 0 b t u o d l t to1 r 1 p 3 m 2 n 2 m 1 n 2 l 1 m d i l a v s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r b l e n n a h c e h t n o d i l a v d n a e d o m k c o l c l l u f n i p b c r f o e g d e g n i s i r e h t n o . e d o m k c o l c f l a h n i n b c r d n a p b c r h t o b f o e g d e g n i s i r b f o el t to1 ls e t a c i d n i t u p t u o s i h t n o h g i h a . d e t c e t e d e m a r f f o d n e b l e n n a h c l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b s a h 5 . 8 2 k d i l a v a t a h t ) . 8 e l b a t e e s ( . ] 7 : 0 [ b t u o d s t u p t u o a t a d b g a l f kl t to2 pa t a h t s e t a c i d n i b g a l f k n i h g i h a . g a l f r e t c a r a h c - k b l e n n a h c e h t n o t n e s e r p a t a d . d e t c e t e d n e e b s a h r e t c a r a h c l o r t n o c d i l a v h c i h w e t a c i d n i o t d e s u e b d l u o h s ] 7 : 0 [ b t u o d e c a f r e t n i l e l l a r a p ) . 8 e l b a t e e s ( . d e v i e c e r s a w r e t c a r a h c b r r el t to3 ke h t s e i f i n g i s b r r e n o h g i h a . r o r r e e v i e c e r b l e n n a h c r o r r e d r o w e d o c d i l a v n i n a r o r o r r e y t i r a p a r e h t i e f o e c n e r r u c c o ) . 8 e l b a t e e s ( . a t a d d e v i e c e r e h t f o g n i d o c e d g n i r u d p b c r n b c r l t to1 u 1 t , b f o e , ] 7 : 0 [ b t u o d , a t a d e v i e c e r l e l l a r a p . k c o l c a t a d e v i e c e r n e h w p b c r f o e g d e g n i s i r e h t n o d i l a v e r a b r r e d n a , b g a l f k d n a p b c r h t o b f o e g d e g n i s i r e h t n o d i l a v d n a e d o m k c o l c l l u f n i . e d o m k c o l c f l a h n i n b c r 23 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g table 12. receiver output signal pin assignment and description (continued) e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 7 c t u o d 6 c t u o d 5 c t u o d 4 c t u o d 3 c t u o d 2 c t u o d 1 c t u o d 0 c t u o d l t to7 r 6 r 5 t 3 u 4 t 5 r 2 u 3 t s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r c l e n n a h c n o d i l a v d n a e d o m k c o l c l l u f n i p c c r f o e g d e g n i s i r e h t n o d i l a v . e d o m k c o l c f l a h n i n c c r d n a p c c r h t o b f o e g d e g n i s i r e h t c f o el t to2 rs e t a c i d n i t u p t u o s i h t n o h g i h a . d e t c e t e d e m a r f f o d n e c l e n n a h c l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b s a h 5 . 8 2 k d i l a v a t a h t ) . 8 e l b a t e e s ( . ] 7 : 0 [ c t u o d s t u p t u o a t a d c g a l f kl t to3 pa t a h t s e t a c i d n i c g a l f k n i h g i h a . g a l f r e t c a r a h c - k c l e n n a h c e h t n o t n e s e r p a t a d . d e t c e t e d n e e b s a h r e t c a r a h c l o r t n o c d i l a v h c i h w e t a c i d n i o t d e s u e b d l u o h s ] 7 : 0 [ c t u o d e c a f r e t n i l e l l a r a p ) . 8 e l b a t e e s ( . d e v i e c e r s a w r e t c a r a h c c r r el t to2 te h t s e i f i n g i s c r r e n o h g i h a . r o r r e e v i e c e r c l e n n a h c r o r r e d r o w e d o c d i l a v n i n a r o r o r r e y t i r a p a r e h t i e f o e c n e r r u c c o ) . 8 e l b a t e e s ( . a t a d d e v i e c e r e h t f o g n i d o c e d g n i r u d p c c r n c c r l t to5 u 4 u , c f o e , ] 7 : 0 [ c t u o d , a t a d e v i e c e r l e l l a r a p . k c o l c a t a d e v i e c e r n e h w p c c r f o e g d e g n i s i r e h t n o d i l a v e r a c r r e d n a , c g a l f k d n a p c c r h t o b f o e g d e g n i s i r e h t n o d i l a v d n a e d o m k c o l c l l u f n i . e d o m k c o l c f l a h n i n c c r 7 d t u o d 6 d t u o d 5 d t u o d 4 d t u o d 3 d t u o d 2 d t u o d 1 d t u o d 0 d t u o d l t to 1 1 u 0 1 r 9 u 9 r 9 t 8 u 7 u 8 t s i s u b s i h t n o a t a d l e l l a r a p . s t u p t u o a t a d r e v i e c e r d l e n n a h c n o d i l a v d n a e d o m k c o l c l l u f n i p d c r f o e g d e g n i s i r e h t n o d i l a v . e d o m k c o l c f l a h n i n d c r d n a p d c r h t o b f o e g d e g n i s i r e h t d f o el t to6 us e t a c i d n i t u p t u o s i h t n o h g i h a . d e t c e t e d e m a r f f o d n e d l e n n a h c l e l l a r a p e h t n o t n e s e r p s i d n a d e t c e t e d n e e b s a h 5 . 8 2 k d i l a v a t a h t ) . 8 e l b a t e e s ( . ] 7 : 0 [ d t u o d s t u p t u o a t a d d g a l f kl t to7 ta t a h t s e t a c i d n i d g a l f k n i h g i h a . g a l f r e t c a r a h c - k d l e n n a h c e h t n o t n e s e r p a t a d . d e t c e t e d n e e b s a h r e t c a r a h c l o r t n o c d i l a v h c i h w e t a c i d n i o t d e s u e b d l u o h s ] 7 : 0 [ d t u o d e c a f r e t n i l e l l a r a p ) . 8 e l b a t e e s ( . d e v i e c e r s a w r e t c a r a h c d r r el t to6 te h t s e i f i n g i s d r r e n o h g i h a . r o r r e e v i e c e r d l e n n a h c r o r r e d r o w e d o c d i l a v n i n a r o r o r r e y t i r a p a r e h t i e f o e c n e r r u c c o ) . 8 e l b a t e e s ( . a t a d d e v i e c e r e h t f o g n i d o c e d g n i r u d p d c r n d c r l t to 0 1 t 0 1 u , d f o e , ] 7 : 0 [ d t u o d , a t a d e v i e c e r l e l l a r a p . k c o l c a t a d e v i e c e r n e h w p d c r f o e g d e g n i s i r e h t n o d i l a v e r a d r r e d n a , d g a l f k d n a p d c r h t o b f o e g d e g n i s i r e h t n o d i l a v d n a e d o m k c o l c l l u f n i . e d o m k c o l c f l a h n i n d c r 24 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g table 13. receiver input signal pin assignment and description e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p a 1 x r n a 1 x r . f f i d l c e p v l i5 d 5 c . a l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a m i r p y l l a n r e t n i . e v i t a g e n e h t s i n a 1 x r , t u p n i e v i t i s o p e h t s i p a 1 x r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b p a 2 x r n a 2 x r . f f i d l c e p v l i4 d 3 b . a l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a d n o c e s y l l a n r e t n i . e v i t a g e n e h t s i n a 2 x r , t u p n i e v i t i s o p e h t s i p a 2 x r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b a l e s x rl t ti3 ah g i h , a 1 x r t u p n i s t c e l e s w o l . l o r t n o c t c e l e s t u p n i a l e n n a h c ) . d e t c e n n o c t o n n e h w p u - l l u p l a n r e t n i ( . a 2 x r s t c e l e s p b 1 x r n b 1 x r . f f i d l c e p v l i6 c 5 b . b l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a m i r p y l l a n r e t n i . e v i t a g e n e h t s i n b 1 x r , t u p n i e v i t i s o p e h t s i p b 1 x r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b p b 2 x r n b 2 x r . f f i d l c e p v l i7 c 7 d . b l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a d n o c e s y l l a n r e t n i . e v i t a g e n e h t s i n b 2 x r , t u p n i e v i t i s o p e h t s i p b 2 x r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b b l e s x rl t ti5 ah g i h , b 1 x r t u p n i s t c e l e s w o l . l o r t n o c t c e l e s t u p n i b l e n n a h c ) . d e t c e n n o c t o n n e h w p u - l l u p l a n r e t n i ( . b 2 x r s t c e l e s p c 1 x r n c 1 x r . f f i d l c e p v l i0 1 a 9 b . c l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a m i r p y l l a n r e t n i . e v i t a g e n e h t s i n c 1 x r , t u p n i e v i t i s o p e h t s i p c 1 x r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b p c 2 x r n c 2 x r . f f i d l c e p v l i8 a 9 a . c l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a d n o c e s y l l a n r e t n i . e v i t a g e n e h t s i n c 2 x r , t u p n i e v i t i s o p e h t s i p c 2 x r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b c l e s x rl t ti9 ch g i h , c 1 x r t u p n i s t c e l e s w o l . l o r t n o c t c e l e s t u p n i c l e n n a h c ) . d e t c e n n o c t o n n e h w p u - l l u p l a n r e t n i ( . c 2 x r s t c e l e s p d 1 x r n d 1 x r . f f i d l c e p v l i0 1 c 0 1 d . d l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a m i r p y l l a n r e t n i . e v i t a g e n e h t s i n d 1 x r , t u p n i e v i t i s o p e h t s i p d 1 x r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b p d 2 x r n d 2 x r . f f i d l c e p v l i1 1 c 2 1 b . d l e n n a h c r o f s t u p n i e l b i t a p m o c l c e p v l l a i t n e r e f f i d y r a d n o c e s y l l a n r e t n i . e v i t a g e n e h t s i n d 2 x r , t u p n i e v i t i s o p e h t s i p d 2 x r . s n o i t a c i l p p a d e l p u o c c a r o f v 3 . 1 - d d v o t d e s a i b d l e s x rl t ti 1 1 bh g i h , d 1 x r t u p n i s t c e l e s w o l . l o r t n o c t c e l e s t u p n i d l e n n a h c ) . d e t c e n n o c t o n n e h w p u - l l u p l a n r e t n i ( . d 2 x r s t c e l e s 25 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g table 14. receiver control signals pin assignment and description e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d n e p ll t ti 4 1 dl a i r e s d e e p s h g i h e h t s i e c r u o s t u p n i , w o l n e h w . e l b a n e k c a b p o o l h c a e r o f t u p t u o l a i r e s e h t , h g i h n e h w . l e n n a h c h c a e r o f t u p n i d e h c l e u q s e r a s t u p t u o a t a d s h . t u p n i s t i o t k c a b d e p o o l s i l e n n a h c . d e l b a n e s i k c a b p o o l n e h w e d o m cl t ti2 cs k c o l c t u p t u o l e l l a r a p e h t , w o l n e h w . l o r t n o c e d o m k c o l c l e l l a r a p e h t , h g i h n e h w . e t a r a t a d e h t 2 / 1 s l a u q e e t a r ) n / p x c r ( . e t a r a t a d e h t o t l a u q e s i e t a r ) n / p x c r ( s k c o l c t u p t u o table 15. power and ground signals pin assignment and description e m a n n i p. y t q# n i pn o i t p i r c s e d a d d v5 6 1 a 3 1 a 6 a 1 a 8 c . ) d e r e t l i f ( e s i o n w o l ) d d v ( r e w o p g o l a n a a s s v5 4 c 5 1 b 8 b 7 b 1 1 d . ) s s v ( d n u o r g g o l a n a d d v5 6 b 4 b 5 1 a 2 1 a 9 d . ) d d v ( y r t i u c r i c d e e p s h g i h r o f r e w o p s s v b u s s s v 0 11 1 a 7 a 4 a 2 a 3 1 c 4 1 b 0 1 b 4 1 a 8 d 6 d ) s s v ( y r t i u c r i c d e e p s h g i h r o f d n u o r g r w p l c e p4 6 1 e 5 1 e 5 1 d 6 1 g . ) d d v ( r e w o p l c e p d n g l c e p26 1 h 6 1 c. ) s s v ( d n u o r g l c e p r w p g i d6 4 l 7 1 j 3 e 2 b 1 b 9 p . ) d d v ( r e w o p y r t i u c r i c e r o c d n g g i d8 5 1 j 4 f 2 d 3 c 1 c 3 r 0 1 p 4 n . ) s s v ( d n u o r g y r t i u c r i c e r o c r w p l t t8 3 n 4 k 4 h 4 g 1 e 8 p 7 p 5 p . ) d d v ( o / i l t t r o f r e w o p d n g l t t0 13 l 4 j 3 f 2 e 1 d 8 r 4 r 6 p 4 p 4 m . ) s s v ( o / i l t t r o f d n u o r g d d v16 1 b. ) v 3 . 3 + ( d d v o t t c e n n o c d n g13 d. ) d n g ( s s v o t t c e n n o c 1 p a c 2 p a c 23 1 d 4 1 c . r o t i c a p a c r e t l i f p o o l l a n r e t x e r o f s n i p 26 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g figure 11. S2065 pinout (bottom view) a b c d e f g h j k l m n p r t u 1 a d d vr w p g i dd n g g i dd n g l t tr w p l t t1 a t u o da r r e4 a t u o d7 a t u o dn a c rb f o e0 b t u o d2 b t u o d6 b t u o d7 b t u o dn b c rp b c r 2 b u s s s vr w p g i de d o m cd n g g i dd n g l t ta f o e0 a t u o d3 a t u o d5 a t u o dp a c r1 b t u o d3 b t u o d4 b t u o db g a l f kc f o ec r r e1 c t u o d 3 a l e s x rn a 2 x rd n g g i dd n gr w p g i dd n g l t ta g a l f k2 a t u o d6 a t u o db r r ed n g l t t5 b t u o dr w p l t tc g a l f kd n g g i d0 c t u o d4 c t u o d 4 s s vd d va s s vp a 2 x rk c o l _ h cd n g g i dr w p l t tr w p l t td n g l t tr w p l t tr w p g i dd n g l t td n g g i dd n g l t td n g l t t3 c t u o dn c c r 5 b l e s x rn b 1 x rn a 1 x rp a 1 x r r w p l t t2 c t u o d5 c t u o dp c c r 6 a d d vd d vp b 1 x rs s v d n g l t t6 c t u o dd r r ed f o e 7 b u s s s va s s vp b 2 x rn b 2 x r r w p l t t7 c t u o dd g a l f k1 d t u o d 8 p c 2 x ra s s va d d vb u s s s v r w p l t td n g l t t0 d t u o d2 d t u o d 9 n c 2 x rn c 1 x rc l e s x rd d v r w p g i d4 d t u o d3 d t u o d5 d t u o d 0 1 p c 1 x rs s vp d 1 x rn d 1 x r d n g g i d6 d t u o dp d c rn d c r 1 1 s s vd l e s x rp d 2 x ra s s v 2 a n i d1 a n i d0 a n i d7 d t u o d 2 1 d d vn d 2 x rl e s k l ce t a r 7 a n i d6 a n i d4 a n i da k l c t 3 1 a d d ve d o m tb u s s s v1 p a c 1 b n i db k l c t5 a n i d3 a n i d 4 1 b u s s s vs s v2 p a cn e p lp a 2 x tp b 2 x tn c 2 x tp d 2 x to k l c t4 d n i dd k l c t5 c n i d0 c n i d6 b n i d4 b n i d0 b n i da n e g k 5 1 d d va s s vt e s e r l c e p r w p l c e p r w p n b 2 x tp c 2 x tn d 2 x td n g g i d5 d n i d0 d n i d7 c n i d2 c n i dc k l c t7 b n i d5 b n i da f o s 6 1 a d d vd d vd n g l c e pn a 2 x t l c e p r w p p c 1 x t l c e p r w p d n g l c e pd f o s6 d n i d2 d n i d1 d n i d6 c n i d3 c n i db f o sb n e g k2 b n i d 7 1 p a 1 x tn a 1 x tp b 1 x tn b 1 x tn c 1 x tp d 1 x tn d 1 x tk l c f e rr w p g i dd n e g k7 d n i d3 d n i dc f o sc n e g k4 c n i d1 c n i d3 b n i d 27 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g figure 12. S2065 pinout (top view) u t r p n m l k j h g f e d c b a 1 p b c rn b c r7 b t u o d6 b t u o d2 b t u o d0 b t u o db f o en a c r7 a t u o d4 a t u o da r r e1 a t u o dr w p l t td n g l t td n g g i dr w p g i da d d v 2 1 c t u o dc r r ec f o eb g a l f k4 b t u o d3 b t u o d1 b t u o dp a c r5 a t u o d3 a t u o d0 a t u o da f o ed n g l t td n g g i de d o m cr w p g i db u s s s v 3 4 c t u o d0 c t u o dd n g g i dc g a l f kr w p l t t5 b t u o dd n g l t tb r r e6 a t u o d2 a t u o da g a l f kd n g l t tr w p g i dd n gd n g g i dn a 2 x ra l e s x r 4 n c c r3 c t u o dd n g l t td n g l t td n g g i dd n g l t tr w p g i dr w p l t td n g l t tr w p l t tr w p l t td n g g i dk c o l _ h cp a 2 x ra s s vd d vs s v 5 p c c r5 c t u o d2 c t u o dr w p l t t p a 1 x rn a 1 x rn b 1 x rb l e s x r 6 d f o ed r r e6 c t u o dd n g l t t s s vp b 1 x rd d va d d v 7 1 d t u o dd g a l f k7 c t u o dr w p l t t n b 2 x rp b 2 x ra s s vb u s s s v 8 2 d t u o d0 d t u o dd n g l t tr w p l t t b u s s s va d d va s s vp c 2 x r 9 5 d t u o d3 d t u o d4 d t u o dr w p g i d d d vc l e s x rn c 1 x rn c 2 x r 0 1 n d c rp d c r6 d t u o dd n g g i d n d 1 x rp d 1 x rs s vp c 1 x r 1 1 7 d t u o d0 a n i d1 a n i d2 a n i d a s s vp d 2 x rd l e s x rs s v 2 1 a k l c t4 a n i d6 a n i d7 a n i d e t a rl e s k l cn d 2 x rd d v 3 1 3 a n i d5 a n i db k l c t1 b n i d 1 p a cb u s s s ve d o m ta d d v 4 1 a n e g k0 b n i d4 b n i d6 b n i d0 c n i d5 c n i dd k l c t4 d n i do k l c tp d 2 x tn c 2 x tp b 2 x tp a 2 x tn e p l2 p a cs s vb u s s s v 5 1 a f o s5 b n i d7 b n i dc k l c t2 c n i d7 c n i d0 d n i d5 d n i dd n g g i dn d 2 x tp c 2 x tn b 2 x t l c e p r w p l c e p r w p t e s e ra s s vd d v 6 1 2 b n i db n e g kb f o s3 c n i d6 c n i d1 d n i d2 d n i d6 d n i dd f o sd n g l c e p l c e p r w p p c 1 x t l c e p r w p n a 2 x td n g l c e pd d va d d v 7 1 3 b n i d1 c n i d4 c n i dc n e g kc f o s3 d n i d7 d n i dd n e g kr w p g i dk l c f e rn d 1 x tp d 1 x tn c 1 x tn b 1 x tp b 1 x tn a 1 x tp a 1 x t 28 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g figure 13. 208 tbga package device S2065 17.7?c/w q ja 3.5?c/w q jc thermal management 29 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g figure 14. transmitter timing (normal or channel lock mode, tmode = 0) table 16. S2065 transmitter timing (normal or channel lock mode, tmode = 0) figure 15. transmitter timing (normal or channel lock mode tmode = 1) table 17. S2065 transmitter timing (normal or channel lock mode, tmode = 1) refclk dinx[0:7], sofx, kgenx t 1 t 2 serial data out tclkx, tclka dinx[0:7], sofx, kgenx t 1 t 2 serial data out s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 1 k l c f e r . t . r . w p u t e s a t a d5 . 0-s n. 1 e t o n e e s t 2 k l c f e r . t . r . w d l o h a t a d3 . 1-s n s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 1 k l c t . t . r . w p u t e s a t a d0 . 1-s n. 1 e t o n e e s t 2 k l c t . t . r . w d l o h a t a d5 . 0-s n 1. all ac measurements are made from the reference voltage level of the clock (1.4v) to the valid input or output data levels (.8v or 2.0v). 1. all ac measurements are made from the reference voltage level of the clock (1.4v) to the valid input or output data levels (.8v or 2.0v). 30 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g figure 16. receiver timing (full clock mode, cmode = 1) table 18. S2065 receiver timing (full clock mode, cmode = 1) figure 17. receiver timing (half clock mode, cmode = 0) table 19. S2065 receiver timing (half clock mode, cmode = 0) rcxn doutx[0:7], eofx, kflagx, errx serial data in t 3 t 4 rcxp s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 3 p x c r . t . r . w p u t e s a t a d 5 7 . 2 5 . 3 -s n s p b g 5 2 . 1 t a s p b g 2 6 0 . 1 t a 1 t 4 p x c r . t . r . w d l o h a t a d0 . 2-s n e l c y c y t u d n / p x c r0 40 6% s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 3 n / p x c r . t . r . w p u t e s a t a d 5 . 2 5 . 3 -s n s p b g 5 2 . 1 t a s p b g 2 6 0 . 1 t a 1 t 4 n / p x c r . t . r . w d l o h a t a d0 . 2-s n e l c y c y t u d n / p x c r0 40 6% rcxn doutx[0:7], eofx, kflagx, errx serial data in rcxp t 3 t 4 t 3 t 4 1. all ac measurements are made from the reference voltage level of the clock (1.4v) to the valid input or output data levels (.8v or 2.0v). 1. all ac measurements are made from the reference voltage level of the clock (1.4v) to the valid input or output data levels (.8v or 2.0v). 31 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g note: measurements are made at 1.4v level of clocks. table 20. S2065 transmitter (tclko timing) figure 18. tclko timing refclk t 5 tclko s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t 5 k l c f e r . t . r . w o k l c t0 . 25 . 7s n e l c y c y t u d o k l c t% 0 4% 0 6% 32 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g table 21. absolute maximum ratings table 22. recommended operating conditions table 23. reference clock requirements r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t e s a c5 5 -5 2 1c ? s a i b r e d n u e r u t a r e p m e t n o i t c n u j5 5 -0 5 1c ? e r u t a r e p m e t e g a r o t s5 6 -0 5 1c ? d n g o t t c e p s e r h t i w d d v n o e g a t l o v5 . 0 -0 . 7 +v n i p t u p n i l t t y n a n o e g a t l o v5 . 0 -7 4 . 3v n i p t u p n i l c e p y n a n o e g a t l o v0d d vv t n e r r u c k n i s t u p t u o l t t8a m t n e r r u c e c r u o s t u p t u o l t t8a m t n e r r u c e c r u o s t u p t u o l c e p d e e p s h g i h0 3a m o / i l t t , e g a t l o v e g r a h c s i d c i t a t s0 0 0 2v o / i l c e p , e g a t l o v e g r a h c s i d c i t a t s0 0 5 1v r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t t n e i b m a00 7c ? s a i b r e d n u e r u t a r e p m e t n o i t c n u j0 3 1c ? o t t c e p s e r h t i w n i p r e w o p y n a n o e g a t l o v s s v / d n g 3 1 . 33 . 37 4 . 3v n i p t u p n i l t t y n a n o e g a t l o v07 4 . 3v n i p t u p n i l c e p y n a n o e g a t l o v d d v v 2 - d d vv s r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n us n o i t i d n o c t fe c n a r e l o t y c n e u q e r f0 0 1 -0 0 1 +m p p d t 2 - 1 y r t e m m y s0 40 6% . t p % 0 5 t a e l c y c y t u d t r c r t , f c r e m i t l l a f d n a e s i r k l c f e r2s n. % 0 8 - % 0 2 r e t t i j0 8s p n i a t n i a m o t , k a e p - o t - k a e p 3 . g n i n e p o e y e % 7 7 33 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g table 24. serial data timing, transmit outputs table 25. serial data timing, receive inputs s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us t n e m m o c r e t t i j l a t o tr e t t i j l a t o t t u p t u o a t a d l a i r e s2 9 1s p. k a e p - o t - k a e p t j d r e t t i j c i t s i n i m r e t e d t u p t u o a t a d l a i r e s0 8s p. k a e p - o t - k a e p t r s t , f s e m i t l l a f d n a e s i r t u p t u o a t a d l a i r e s0 0 3s pk 5 . 4 . % 0 8 - % 0 2 w . d n u o r g o t s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us t n e m m o c t p r t , p f s e m i t l l a f d n a e s i r p x c r0 . 3s n. 0 2 e r u g i f e e s t n r t , n f s e m i t l l a f d n a e s i r n x c r0 . 3s n. 0 2 e r u g i f e e s t r d t , f d s e m i t l l a f d n a e s i r x t u o d0 . 3s n. 9 1 e r u g i f e e s t k c o l ) y c n e u q e r f ( e m i t k c o l n o i t i s i u q c a y c n e u q e r f ) s p b g 5 2 . 1 ( ) k c o l f o s s o l ( 5 7 1s e l p m a s n r e t t a p e l d i b 0 1 / b 8 . p u t r a t s e c i v e d m o r f , s i s a b t k c o l ) e s a h p ( e m i t k c o l n o i t i s i u q c a e s a h p ) s p b g 5 2 . 1 ( ) y t i u n i t n o c s i d e s a h p ( 0 5 1s n e e s ( e y e a t a d t u p n i % 0 9 . ) 4 2 e r u g i f 0 8 1s n. e y e a t a d t u p n i % 0 7 r e t t i j t u p n i e c n a r e l o t r e t t i j l a t o t t u p n i a t a d l a i r e s e c n a r e l o t 9 9 5s p y b d e i f i c e p s s a , k a e p - o t - k a e p . z 3 . 2 0 8 e e e i t j d e c n a r e l o t r e t t i j t u p n i c i t s i n i m r e t e d0 7 3s p r r s r , f s e m i t l l a f d n a e s i r t u p n i a t a d l a i r e s0 5 3s p. % 0 8 - % 0 2 e s i r n x c r o t e s i r p x c r m o r f e m i t 8 . 72 8 . 8s n. s p b g 5 2 . 1 t a 3 . 94 . 0 1s n. s p b g 2 6 0 . 1 t a 34 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g table 26. dc characteristics s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v h o ) l t t ( e g a t l o v h g i h t u p t u o4 . 28 . 2d d vv i n i m = d d v h o a m 4 - = v l o ) l t t ( e g a t l o v w o l t u p t u od n g5 2 0 .5 . 0v i n i m = d d v l o a m 4 = v h i ) l t t ( e g a t l o v h g i h t u p n i0 . 2v v l i ) l t t ( e g a t l o v w o l t u p n id n g8 . 0v i h i ) l t t ( t n e r r u c h g i h t u p n i0 4a v n i x a m = d d v , v 4 . 2 = i l i ) l t t ( t n e r r u c w o l t u p n i0 0 6a v n i x a m = d d v , v 8 . 0 = d d it n e r r u c y l p p u s0 2 80 8 9a m. n r e t t a p 0 1 0 1 p d n o i t a p i s s i d r e w o p7 . 24 . 3w . n r e t t a p 0 1 0 1 v f f i d g n i w s e g a t l o v t u p n i l a i t n e r e f f i d . n i m s t u p n i l c e p l a i t n e r e f f i d r o f 0 0 10 0 2 2v m. 2 2 e r u g i f e e s d v t u o e g a t l o v t u p t u o l a i r e s l a i t n e r e f f i d g n i w s 0 0 2 10 0 9 10 0 2 2v m k 5 . 4 h t i w d e l p u o c c a w l l u p 0 0 1 d n a n w o d w l a i t n e r e f f i d . 1 2 e r u g i f e e s . n o i t a n i m r e t c n i e c n a t i c a p a c t u p n i5 . 13f p 35 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g output load the S2065 serial outputs require a resistive load to set the output current. the recommended resistor value is 4.5 k w to ground. this value can be varied to adjust drive current, signal voltage swing, and power usage on the board. acquisition time with the input eye diagram shown in figure 24, the S2065 will recover data with 1e-9 ber within the time specified by t lock in table 25 after an instan- taneous phase shift of the incoming data. figure 22. high speed differential inputs figure 19. serial input/output rise and fall time figure 23. receiver input eye diagram jitter mask figure 20. ttl input/output rise and fall time figure 21. serial output load figure 24. acquisition time eye diagram t r t f 80% 20% 50% 80% 20% 50% t r t f +2.0v +0.8v +2.0v +0.8v 4.5 k 4.5 k 0.01 f 0.01 f 100 0.01 f 0.01 f vcc - 1.3 v bit time amplitude 24% 1.3 normalized amplitude normalized time 1.0 0.0 0.2 0.3 0.5 0.7 0.8 0.1 0.6 0.4 0.3 0.7 0.9 1.0 0.0 36 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g figure 25. loop filter capacitor connections cap1 270 22 nf cap2 270 S2065 37 S2065 quad serial backplane device with dual i/o october 13, 2000 / revision g ordering information x xxxx x prefix device package x i f e r pe c i v e de g a k c a p t i u c r i c d e t a r g e t n i - s5 6 0 2a g b t 8 0 2 C a amcc is a registered trademark of applied micro circuits corporation. copyright ? 2000 applied micro circuits corporation d88/r251 amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr., san diego, ca 92121 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1 |
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